<b>Overview</b><br><p style="margin: 0in 0in 8pt; line-height: 107%; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif; color: black;">Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is the team behind Microsoft’s expanding Cloud Infrastructure and responsible for powering Microsoft’s “Intelligent Cloud” mission. SCHIE delivers the core infrastructure and foundational technologies for Microsoft's over 200 online businesses including Bing, MSN, Office 365, Xbox Live, Teams, OneDrive, and the Microsoft Azure platform globally with our server and data center infrastructure, security and compliance, operations, globalization, and manageability solutions. Our focus is on smart growth, high efficiency, and delivering a trusted experience to customers and partners worldwide and we are looking for passionate engineers to help achieve that mission.</span></p><p style="margin: 0in 0in 8pt; line-height: 107%; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif; color: black;">The Compute Silicon & Manufacturing Engineering (CSME) organization within SCHIE is responsible for design, development, manufacturing and packaging of Microsoft's state-of-the-art computer chips, notably the Azure Cobalt. Our solutions provide sustainable strategic advantage to Microsoft and enable our customers to achieve more.</span></p><p style="margin: 0in 0in 8pt; line-height: 107%; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif; color: black;">As Microsoft's cloud business continues to grow the ability to deploy new offerings and hardware infrastructure on time, in high volume with high quality and lowest cost is of paramount importance. To achieve this goal, <strong>Verification & Validation </strong>team is instrumental in defining and delivering operational measures of success for hardware manufacturing, improving the planning process, quality, delivery, scale and sustainability related to Microsoft cloud hardware. We are looking for seasoned engineers with a dedicated passion for customer focused solutions, insight and industry knowledge to envision and implement future technical solutions that will manage and optimize the Cloud infrastructure. </span></p><p style="margin: 0in 0in 8pt; line-height: 107%; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif; color: black;"> We are looking for a <strong>Senior SOC Debug Verification Engineer</strong> to join the team.</span></p><p style="margin: 0in; line-height: normal; font-size: 11pt; font-family: Calibri, sans-serif;"> </p><p style="margin: 0in; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">#SCHIE #CSME </span></p><br><br><b>Responsibilities</b><br><p style="line-height: normal; background-color: white; margin: 0in 0in 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><strong><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">The candidate for this position will be expected and able to complete the following responsibilities:</span></strong></p><ul style="margin-bottom: 0in; margin-top: 0px;" type="disc"><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Own verification of Design for Debug (DFD) SoC level flows including Task planning and schedule estimation, proactively identifying and removing roadblocks and finding ways to make the team more efficient</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Develop verification strategy, requirements, environments, tools, and methodologies</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Become an expert on the overall debug architecture, understand customer use models, and understand interactions with other parts of the SOC, with the platform, and with software</span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Apply your knowledge of verification principles and techniques and your judgement to write test plans and implement them by developing tests, test generators, test benches, checkers, coverage, and other verification collateral</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Run tests, debug failures to root cause, and recommend fixes</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Apply your growth mindset to learn and adapt in a complex and dynamic environment</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Engage with partners to drive continuous improvement to both the design, to verification plans/collateral, and to methodology to prevent, reduce, and/or find bugs sooner, more easily, or more reliably</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Provide technical guidance, coaching, and mentorship to other engineers in your areas of expertise</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Apply your One Microsoft mentality to collaborate with and influence architects, logic designers, post-silicon validators, other verification engineers, and IP and tool providers </span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Delight your customers by providing high quality results on schedule</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Provide technical leadership with respect and integrity</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Apply your expertise towards supporting the post-silicon validation plans, tests, and debug of your area</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li><li style="line-height: normal; background-color: white; margin-top: 0in; margin-right: 0in; margin-bottom: 8pt; font-size: 11pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;">Apply industry leading generative AI solutions to verification work</span><span style="font-size: 10.0pt; font-family: Verdana, sans-serif; color: black;"> </span></li></ul><br><br><b>Qualifications</b><br><p style="margin: 0.0in 0.0in 8.0pt; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><strong><u><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Required Qualifications:</span></u></strong></p><ul style="margin-bottom: 0.0in; margin-top: 0.0px;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">8+ years of pre-silicon SOC or subsystem or IP verification experience. </span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Candidate must have at least a bachelor’s or master’s degree in electrical, Electronics, Computer Engineering, Computer Science or a related degree </span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 8.0pt 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">6+ years of verification experience working on CPU/SOC designs, with 2+ years of design for debug verification experience </span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li></ul><p style="margin: 0.0in 0.0in 8.0pt; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"> </p><p style="margin: 0.0in 0.0in 8.0pt; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><strong><u><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Preferred Qualifications:</span></u></strong></p><ul style="margin-bottom: 0.0in; margin-top: 0.0px;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Experience with SOC DFD verification for a full product cycle from definition to silicon, including writing SOC level test plans, developing tests, debugging failures and coverage signoff</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Demonstrated expertise in industry standard DFD architectural protocols such as JTAG interface, hardware triggers, breakpoints and tracing and h</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">ands-on experience in <strong>ARM Core Sight debug</strong></span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Experience enabling and/or utilizing debug features in post-silicon</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Proficient communication, collaboration and teamwork skills and ability to contribute to diverse and inclusive teams</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Experience planning verification tasks, estimating and assigning tasks, coordinating with customers and suppliers, and executing the plan</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Proficient leadership skills</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Passion for improving verification efficiency</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li><li style="margin: 0.0in 0.0in 8.0pt 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Experience with Agile software practices</span><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;"> </span></li></ul><p style="margin: 0.0in 0.0in 8.0pt; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"> </p><p style="margin: 0.0in 0.0in 8.0pt; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><strong><u><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Screening Requirements</span></u></strong></p><ul style="margin-bottom: 0.0in; margin-top: 0.0px;"><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">Ability to meet Microsoft, customer and/or government security screening requirements are required for this role. These requirements include but are not limited to the following specialized security screenings: Microsoft Cloud Background Check: This position will be required to pass the Microsoft Cloud Background Check upon hire/transfer and every two years thereafter. </span></li><li style="margin: 0.0in 0.0in 0.0in 0.0px; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"><span style="font-size: 10.0pt; line-height: 107%; font-family: Verdana, sans-serif;">This role will require access to information that is controlled for export under export control regulations, potentially under the U.S. International Traffic in Arms Regulations or Export Administration Regulations, the EU Dual Use Regulation, and/or other export control regulations. As a condition of employment, the successful candidate will be required to provide either proof of their country of citizenship or proof of their US. residency or other protected status (e.g., under 8 U.S.C. 1324b(a)(3)) for assessment of eligibility to access the export-controlled information. To meet this legal requirement, and as a condition of employment, the successful candidate’s citizenship will be verified with a valid passport. Lawful permanent residents, refugees, and asylees may verify status using other documents, where applicable.</span></li></ul><p style="margin: 0.0in 0.0in 8.0pt 0.5in; line-height: 107%; font-size: 11.0pt; font-family: Calibri, sans-serif;"> </p> <br><p>This position will be open for a minimum of 5 days, with applications accepted on an ongoing basis until the position is filled.</p><br><hr><br><p>Microsoft is an equal opportunity employer. All qualified applicants will receive consideration for employment without regard to age, ancestry, citizenship, color, family or medical care leave, gender identity or expression, genetic information, immigration status, marital status, medical condition, national origin, physical or mental disability, political affiliation, protected veteran or military status, race, ethnicity, religion, sex (including pregnancy), sexual orientation, or any other characteristic protected by applicable local laws, regulations and ordinances. If you need assistance with religious accommodations and/or a reasonable accommodation due to a disability during the application process, read more about <a href="https://careers.microsoft.com/v2/global/en/accessibility.html"><b><u>requesting accommodations.</u></b></a></p>